SystemVerilog FrameWorks™ Template Generator (SVF-TG) is a tool for generating a detailed boilerplate for a UVM based verification environment from scratch based on user input.

- Generates UVCs and Testbenches

- Includes makefile that operates with Synopsys, Cadence and Mentor simulators

- Generates code that operates with either the SV package technique or include technique

- Generates virtual sequences and scoreboards

- Options for controlling the name of the project, tests, UVCs, number of agents, and bus monitors

The generated code is compilable with the following tools/versions:

- Cadence IUS 09.20-014 or later

- Mentor QuestaSim 6.6a-1 or later

- Synopsys VCS 2010.06-B or later

- UVM 1.0 EA

Please contact info@paradigm-works.com for further information.